Optical and electrical interconnect economics through 2030. Goldman’s $154B optical TAM unpacked, with services unbundled — network test, hyperscale fit-out, fiber MSPs all surface as exposed names.
This primer addresses a reader who knows the AI capex story at the level of "GPUs are big, hyperscalers are spending a trillion dollars" but does not yet have the vocabulary for the networking layer of that stack. By the end, the reader will be able to: distinguish scale-up, scale-out, and scale-across; recognize CPO, LPO, NPO, OCS, and DCI as discrete sub-markets with different winners; place every architectural alternative to NVIDIA (Cerebras, Groq, SambaNova, Google TPU, AWS Trainium, AMD, Intel, Microsoft Maia, Meta MTIA) inside the networking thesis; and name the public-and-private companies that benefit at each layer.
The anchor question this primer answers: if the AI buildout keeps moving faster than consensus, where is the networking layer's marginal dollar going, and who collects it?
The AI data-center capex story is no longer "buy more GPUs." It has been a bottleneck-progression story for at least three years: the binding constraint moves from one layer of the stack to the next, and capex re-allocates to whichever link is currently binding. Roughly: 2022-2024 was GPU compute (TSMC CoWoS packaging was sold out); 2024-2025 was HBM memory (High Bandwidth Memory — the stack of DRAM dies that sits next to each GPU; sold out, with reported price increases of +246% year-over-year 1); 2025-2026 is optical interconnect, where copper interconnect has reached a physical limit and scale-up requires fiber; 2026 onward is power and liquid cooling, where per-rack power has gone from 10-20 kW in the CPU era to 120-200 kW+ in the AI era 1, and the air-cooling physical limit (20-50 kW per rack) forces a switch to liquid above that threshold.
This bottleneck-progression framing has two well-articulated formulations in the literature, and the primer's thesis sits on top of both:
Bernstein 97-page interconnect report (May 2026) [S066, S067, S068]. Bernstein argues that the next phase of AI capital expenditure shifts focus from raw GPU shipments toward the interconnect capabilities that let GPUs work together — and quantifies the shift in per-GPU dollar content. HDI+PCB content per GPU rises from roughly $100-150 (H100 era) to $300 (GB200 NVL72) [S066, S067], and Rubin Ultra introduces a 78-layer M9 CCL midplane PCB at roughly $112,500 per unit, two units per rack 2.
PANews bottleneck-transmission article (May 22, 2026) [S062, S064, S074, S075, S076]. Same idea formalized as a Leontief production function: GPU, HBM, interconnect, power, and cooling are complements that must be matched on the lowest-weakest-link. Each year's shift in the binding constraint reshapes capex allocation across the stack.
Both formulations give the deliverable's value its anchor. The work this primer does on top of them is to (a) ground the networking-specific claims in a bottoms-up component taxonomy, (b) cross-check against Goldman Sachs's $154B optical-networking TAM forecast for 2028 [S001, S002, S003], and (c) extend the chain into the chip-maker architectural alternatives and the agentic-CPU phenomenon, where independent signals reinforce the thesis from outside the original report set.
The headline number, before we walk the stack: Goldman Sachs forecasts a 9x increase in the aggregate optical-networking TAM, from $15B in the GB300 NVL72 generation (2026) to $154B in the Rubin Ultra NVL576 generation (2028) [S001, S002], with 69% of that prize landing in scale-up (intra-rack and intra-supernode) optical 2 and co-packaged optics (CPO) capturing 59% of the total at just 29% scale-out CPO penetration [S005, S006]. The per-rack scale-up content increases 5.7x from $140K (GB300) to $803K (Rubin Ultra Spec B) [S012, S013]; per-computing-unit content increases 29x from $315K to $9.4M [S007, S008, S009]. The thesis is not that the optical layer grows in line with GPU shipments — it is that the optical layer grows faster than GPU shipments per unit of compute because the architecture itself is changing.
What follows is the pedagogical center of the primer: every layer of the AI-DC networking stack, defined first, then quantified. The eight layers form a coherent physical hierarchy from the silicon die outward to the long-haul fiber ring.
Definition. Communication inside a single accelerator package, or between dies on the same silicon substrate. Two flavors: die-to-die within a single accelerator (the two-die Blackwell GPU; TSMC's CoWoS-S/L packaging), and chip-to-chip across a package (NVLink between GPUs, NVLink-C2C between Grace CPU and Hopper/Blackwell GPU, AMD's Infinity Fabric, and the HBM memory bus itself).
Key numbers. NVLink 5 (Blackwell, 2024) carries 7.2 Tbit/s unidirectional per GPU 2; NVLink 6 (Vera Rubin, 2026) doubles that to 14.4 Tbit/s per GPU 2. The underlying SerDes — the analog circuit that drives the cable — moves from 224 Gbps lanes in NVLink 5 to 400 Gbps in NVLink 6 2. Each B200 GPU now carries roughly 192 GB of HBM3e memory; an NVL72 rack therefore aggregates approximately 14 TB of HBM at the chip level (per-GPU figure scales as the GPU generation progresses).
Why it matters now. Compute die area is at the reticle limit set by lithography; further training and inference gains must come from packing more accelerators into a tight scale-up domain. Every die-to-die generation doubles per-GPU bandwidth, which forces the next layer of interconnect to keep pace.
What's changing. Standards are bifurcating. NVIDIA's NVLink is proprietary. The open alternatives — UALink 1.0 (May 2025 spec) and ESUN/SUE-T (August 2025) 2 — entered the field in 2025, backed by a broad consortium of AMD, Arista, Broadcom, Cisco, HPE, Intel, Meta, Microsoft, NVIDIA itself, OpenAI, and Oracle. The same open-vs-closed dynamic that played out at scale-out (Ethernet vs InfiniBand) is now repeating at scale-up.
Definition. A scale-up domain is the set of accelerators that the workload sees as one big logical accelerator: every GPU connects to every other GPU via NVLink (or equivalent), single-hop, with shared memory semantics. Historically a scale-up domain was 8 GPUs (the HGX baseboard). Today it is 72 (NVL72). By 2027 it will be 576 (Rubin Ultra NVL576 in Spec B configuration), spanning 8 racks as one unit 2.
Key numbers. A GB200/GB300 NVL72 rack contains 72 GPUs, 18 NVLink switch ASICs (Application-Specific Integrated Circuits — the silicon that performs the actual packet switching), 72 network interface cards (NICs), and is wired together with 5,184 copper cables per rack in what NVIDIA calls the Oberon backplane [S015, S080]. Rubin Ultra Kyber NVL144 (2027) keeps the rack at 144 GPUs but replaces the copper backplane with a 78-layer M9 CCL printed-circuit-board midplane priced at approximately $112,500 per unit, with two units per rack — about $225K of PCB content per rack [S049, S050]. The Spec B Rubin Ultra NVL576 (2028) connects 8 Oberon racks as a single computing unit; the first layer of scale-up stays copper inside each rack, but the second layer (rack-to-rack) uses co-packaged optics with optical engines and FAUs (fiber array units), eliminating pluggable optical transceivers in that layer.
Why it matters now. Scale-up is where $106B (69%) of the new $154B optical TAM lives by 2028 [S003, S004]. Per-rack scale-up content moves 5.7x from $140K to $803K [S012, S013] across the GB300-to-Rubin-Ultra transition; per-computing-unit content moves 29x from $315K to $9.4M [S007, S008, S009]. A single scale-up domain — what was "a rack" two years ago — now requires nearly $10M of optical content alone.
What's changing. The "computing unit" is no longer "one rack." Scale-up extends across 8 racks via CPO. Rack-internal copper backplane, intra-rack PCB midplane, and rack-to-rack CPO together form one continuous networking fabric, not three separate things. This is the central architectural inflection.
A spectrum of how tightly the optical engine couples to the switch ASIC or accelerator silicon.
Key numbers. A 1.6T pluggable transceiver burns about 30W, roughly half of which is the DSP 3. NVIDIA's CPO optical engine, by contrast, runs at 4-5W per 800G 4 — about a 73% power reduction versus pluggable. Broadcom's Bailly 51.2T CPO switch is 5.4W per 800G 4. The reliability gap is also large: a Meta ECOC 2025 study found CPO MTBF (mean time between failures) of 2.6 million device hours, versus 0.5-1M for 400G pluggables — a 2.6 to 5.2x improvement 4.
The NVIDIA Quantum-X800 CPO switch BoM contains 72 optical engines, 18 external laser sources, and 4 switch ASICs, totaling a $75,803 bill of materials at a $130K selling price (Goldman Sachs estimate) [S021, S022]. Note: Bernstein cites the same switch at roughly $570K 3; the gap likely reflects different system scope (Bernstein may include the fully-loaded chassis with PSUs and integration markup). Until reconciled, treat any quoted per-unit number as scope-dependent.
CPO adoption timing: NVIDIA Quantum-X CPO went commercial GA in early 2026 2; Broadcom's Davisson 102.4T CPO switch sampled in October 2025 and volume-ships through 2026 [S020, S099]; Marvell will sample CPO in 2027 2. CPO for accelerators themselves (XPU-side, not switch-side) does not arrive in volume until 2028+, with the schedule "still unclear" per Goldman 3. LPO is the dark-horse alternative — Bernstein projects that LPO shipments could surpass CPO by 2030 3.
Why it matters now. Per Goldman's framework, CPO alone contributes $91B to the $154B 2028 TAM [S005, S006] at just 29% scale-out CPO penetration. The high-end CPO TAM across 2026-2028 sums to $97B 2; annual CPO switch shipments reach 110K units in 2028 2; the optical-engine market itself reaches 40 million units per year by 2028 2. CPO is the largest single new component category in AI-DC capex.
What's changing. The profit pool reallocates. Pluggable-module vendors (Innolight, Coherent, Eoptolink, Lumentum at the module level) are forced into one of two paths: either become the optical-engine supplier inside a CPO package (selling sub-assemblies to a chip designer who owns the integration), or transition to the lower-cost LPO/SiPh segment where pluggability still matters. Chip designers (TSMC COUPE, Broadcom Bailly/Davisson, NVIDIA Quantum-X/Spectrum-X), advanced packagers (TSMC ASE Foxconn JCET), light-source suppliers (Sumitomo, Furukawa, Landmark, VPEC), FAU/MPO connector specialists (FOCI, Senko, Corning, Sumitomo), and test/yield equipment makers (Keysight, Teradyne, Advantest, FormFactor, MPI Corp) capture more of the value 3. Marvell's acquisition of Celestial AI (closed February 2026) is the pure-play "CPO for accelerators" bet [S079, S304, S305] — Celestial AI targets a $1B run-rate by 2028 4.
Definition. The fabric that connects clusters of scale-up domains (racks) into a unified compute fabric across a single data-center building. Two competing technology stacks:
Key numbers. A 3-layer scale-out network supports about 18,432 GPUs per cluster 2; the industry is now pushing 100,000+-GPU clusters with denser fabrics. The optical-module migration path runs 800G → 1.6T → 3.2T → 6.4T: 1.6T entered mass-volume in Q4 2025 at about 11% market share 2; reaches 35% mainstream by Q3 2027 2; 3.2T enters mass-volume in late 2026 / early 2027 2. Optical-transceiver attach ratio per GPU climbs from 1:2-3 on GB300 2 to 1:4-6 on Vera Rubin VR200 2, and as high as 1:18 (all-optics) on Huawei's CloudMatrix 384 2 — meaning the ratio of fiber connections per GPU grows materially as the cluster topology becomes denser.
A 1.6T silicon-photonics module is priced at $800 ASP with $341 BoM and 57% gross margin, versus the older EML-based 1.6T at $1,000 ASP / $500 BoM / 50% gross margin — a 20% price advantage and a 32% BoM advantage for SiPh 2. Switch ASIC capacity: Tomahawk 5 = 51.2 Tb/s, Tomahawk 6 Davisson = 102.4 Tb/s 2, Quantum-X Photonics = 115.2 Tb/s, Spectrum-X Photonics = 409.6 Tb/s 2.
Why it matters now. Scale-out captures the remaining 31% of the $154B 2028 TAM (about $48B). It is also the first beachhead for CPO — switch-side CPO ships 2026 while XPU-side CPO waits until 2028+. The InfiniBand-vs-Ethernet standards war determines who captures share inside that $48B.
What's changing. Open Ethernet (UEC + Tomahawk 6 + AMD/Arista/Cisco/HPE) is the cost-effective challenger to NVIDIA InfiniBand. Silicon-photonics penetration in datacom transceivers climbs from 6% in 1Q24 to 46% in 4Q28E per Goldman [S023, S024]: silicon photonics displaces traditional EML-based transceivers as the volume rises.
Definition. The newest and least-mapped tier: connecting servers across data centers in different physical locations. Goldman defines this tier (in the $154B TAM report, Exhibit 47) as the new scale-across layer beyond intra-DC scale-out; NVIDIA introduced its scale-across product line in 2025 via in-house Ethernet switches and NICs 2.
Why it's a new tier. Hyperscalers are running out of contiguous power within single campuses. Multi-campus training runs (rumored Microsoft + OpenAI multi-site clusters; Google's distributed regions; Meta's distributed-training experiments) require: long-haul optical fiber rings, DWDM/coherent transceivers (400G/800G/1.6T coherent ZR/ZR+/ZR++ — industry-standard distance grades for coherent optical interfaces, with ZR carrying ~80km, ZR+ ~400km, ZR++ ~1,000km+), low-latency hollow-core fiber where applicable, and DCI-specific edge devices from Ciena, Infinera, Nokia, or Cisco.
Key numbers. Hollow-core fiber transmits at the speed of light in vacuum — 298,301 km/sec — versus glass-core fiber at 204,190 km/sec, a 46% latency advantage 2. Prysmian (the largest global cable maker; 8% of revenue from fiber, with Digital Solutions 16% data-center exposure 2) is developing 160-micron bend-insensitive hollow-core fiber, has signed long-term framework agreements with hyperscalers, and reports its fiber order book sold through 2026. The physical breakpoints between scale-up, scale-out, and scale-across are governed by reach limits: up to 3 meters for Direct Attach Copper 2, 30 meters for Active Electrical Cable 2, 2 kilometers for FR optical 2 — anything longer requires DCI.
Why it matters now. Scale-across is where Prysmian, Corning, Furukawa Electric, YOFC, and the long-haul telecom carriers (Lumen, Zayo, Cogent, and the remains of Crown Castle's old fiber footprint) participate. Today's scale-across spend is small (a couple of billion dollars annually) but the trajectory is steep as multi-site training builds. Crucially, Goldman's $154B TAM does not include scale-across fiber, DCI coherent optics, or outside-plant capex — that is a separate (smaller but fast-growing) bucket.
Definition. A switch that operates entirely in the optical domain — no electrical-to-optical-to-electrical (OEO) conversion. Light enters, light exits; the switch is reconfigurable via MEMS mirrors (Google's Palomar / Apollo), liquid crystal on silicon (Coherent), piezo-actuated beam steering (Huber+Suhner Polatis), or silicon-photonic switch fabrics (Innolight, iPronics — both still in qualification).
Key numbers. Google's TPU v4 (2023) used 4,096 chips interconnected by 48 internally-developed OCS switches 2; TPU v7 SuperPod (2025) connects 9,216 chips via OCS 2. Lumentum's OCS backlog exceeded $400M as of February 2026 [S032, S093]; Coherent reports more than 10 customers engaged 2, shipping 64×64 and 320×320 systems. OCS switch ASPs range from $50K-$200K 2 versus $10K-$100K for traditional electrical switches. The defining future-proofing advantage: OCS does not need replacement when port speeds upgrade (800G → 1.6T → 3.2T), because the switch is rate-agnostic.
The Open Compute Project announced a formal OCS initiative in 2025 with Lumentum, iPronics, Google, NVIDIA, Coherent, and Microsoft. Innolight targets silicon-photonic OCS in 2027.
Why it matters now. Beyond Google, OCS hits real adoption in 2026. Hyperscalers view OCS as a way to dynamically rewire training topology without rebuilding the fabric — particularly valuable for variable-shape workloads (the same physical cluster runs different training jobs without recabling). Four technology branches (MEMS, LCoS, Piezo, SiPh) 2 compete on switching time, reliability, insertion loss, and port count.
Definition. Dark fiber is installed fiber-optic cable that has not been "lit" — the buyer or lessee lights it themselves with their own DWDM transceivers. Most of the current dark-fiber inventory was over-built by telecoms during the 1990s dot-com era and is now being repurposed for hyperscaler DC-to-DC needs. Outside-plant is the construction layer underneath: trenching, conduit placement, cable splicing, cabinet installation, last-mile to the data center.
Why it matters now. With scale-across emerging as a real tier, hyperscalers are leasing dark fiber from Zayo, Lumen, Cogent, and FiberLight, then lighting it with their own DWDM, rather than buying lit wavelengths from the carriers. Microsoft, Google, and Meta have each confirmed multi-billion-dollar long-term fiber-lease commitments. Lumen alone closed approximately $13B in Private Connectivity Fabric (PCF) deals during FY25 with Microsoft, Meta, and others.
The construction layer — Quanta Services, MasTec, Dycom, Centuri — physically builds the fiber routes. These are capex-equity stories trading off the build cycle, not the data-flow cycle.
Goldman's $154B optical-networking TAM excludes the outside-plant capex by design.
Definition. The chip inside the switch box that does the packet switching. Three architectural classes:
Key numbers. Tomahawk 6 Davisson runs 102.4 Tb/s on 200G-per-lane SerDes — either 64 ports of 1.6T or 128 ports of 800G 2. NVIDIA Quantum-X800 runs 115.2 Tb/s across 4 ASICs of 28.8 Tb/s each, 144 ports of 800G [S018, S056]. Spectrum-X Photonics runs 409.6 Tb/s on four 102.4 Tb/s ASICs, supporting 512 ports of 800G 2.
Why it matters now. Switch ASICs are the highest-margin silicon in the network. Broadcom's networking franchise is estimated to contribute more than $10B of 2027 EPS. Marvell and Astera Labs are growing rapidly. Cisco is attempting to recapture share via Silicon One. The Anthropic-Broadcom $21B order commitment 5 is the single largest external custom-ASIC validation outside Google TPU. Broadcom is the most direct public-equity exposure to the optical and CPO TAM expansion because it sells both the switch ASIC and the Bailly/Davisson CPO platform on top of it.
What's changing. The CPO transition reshapes who captures the value at the ASIC layer. In a pluggable world, Broadcom sold the $30K Tomahawk and the optical vendor sold the $2K transceiver. In a CPO world, the same dollar value moves into the package Broadcom designs — Broadcom absorbs the optical engine's economics directly, or sells the bare CPO-ready ASIC and lets TSMC capture the packaging margin. Bernstein's framing: CPO fundamentally reshapes the value chain, shifting profit centers away from traditional optical-module suppliers toward chip designers, advanced packaging providers, and system integrators 3.
The default assumption in the optical TAM forecasts is that NVIDIA's stack continues to be the dominant architecture. That assumption is contestable. Below is the architectural-alternative landscape: what each chip-maker actually does, where it has won customers, and what it implies for the networking layer. The verdict at the bottom of each entry is grounded in what the architecture is, not in the architectural-alternative provider's marketing claims.
Architecture. Cerebras's Wafer-Scale Engine 3 (WSE-3) is a single 5-nanometer chip the size of a dinner plate: 4 trillion transistors, 900,000 AI cores, 125 petaflops of peak AI performance per chip [primary: 2024-03-13 Cerebras + G42 press release]. The architecture collapses what would otherwise be 50+ discrete GPUs into one piece of silicon. The on-wafer interconnect runs at 214 Pb/s, while chassis-to-chassis scale-out I/O is only 1.2 Tb/s [S102, S103] — a ~178,000:1 ratio.
Deployment. The flagship deployment is Condor Galaxy, a partnership with G42 (UAE). Condor Galaxy 3 (Dallas, Texas, Q2 2024) is 64 CS-3 systems delivering 8 exaFLOPs; together with CG-1 and CG-2 the network totals 16 exaFLOPs. Cerebras's S-1 disclosed 86% revenue concentration in two UAE entities — G42 at 24% and MBZUAI at 62% of 2025 revenue 6.
Networking impact. Cerebras is the one architecture in this entire landscape that genuinely collapses networking demand inside the system. The 178,000:1 ratio means chassis-to-chassis fiber demand per FLOP is dramatically lower than equivalent GPU clusters. The complication: Cerebras has a DARPA-funded partnership with Ranovus to integrate wafer-scale co-packaged optics (announced 2025), targeting 100x current CPO capacity [S111, S150]. So Cerebras isn't eliminating optical TAM — it is relocating it from pluggable transceivers and InfiniBand switches into wafer-edge CPO. Different winners (Ranovus, Coherent's CPO business, Lightmatter's CPO business); fewer pluggables.
Verdict. If Cerebras grew to 30% share by 2030, it would shrink Goldman's $154B optical-networking TAM, with a strong directional pull (-30 to -40% on the per-FLOP optical figure). The cap on that risk is the customer concentration: 86% in two UAE entities is not a base for scaling to 30% of global AI compute by 2030.
Architecture. Groq's Language Processing Unit (LPU) is a programmable streaming architecture with on-chip SRAM at roughly 80 TB/s of bandwidth versus about 8 TB/s for GPU off-chip memory — a 10x bandwidth advantage [primary: Groq LPU page] 7. The design is deterministic: every execution step is predictable to the smallest cycle, with no synchronization overhead. There is no HBM; everything runs from SRAM.
Deployment. Groq sells inference-as-a-service plus cloud chips. The architecture is constrained: each LPU carries only about 230 MB of SRAM, so serving Llama-70B requires roughly 576 chips stitched together. NVIDIA has moved to absorb Groq's deterministic-SRAM architecture into its broader AI factory stack via a non-exclusive licensing arrangement and asset purchase announced in late 2025 8.
Networking impact. Groq is the opposite of Cerebras: the same model that runs on 1 wafer-scale Cerebras chip runs on ~576 Groq LPUs, stitched together with high-bandwidth intra-rack networking. The architecture reinforces intra-rack networking density per FLOP, with a different latency profile (low-jitter, predictable). NVIDIA's acquisition absorbs Groq's deterministic-execution model into the same vertically integrated stack — the optical TAM Groq drives flows back to NVIDIA-aligned suppliers.
Verdict. If Groq's architecture (whether sold as Groq or as a future NVIDIA SKU) reached 30% inference share, optical TAM shifts — short-reach intra-rack optics up, long-haul scale-across down. Net neutral on aggregate TAM dollars, but mix changes meaningfully.
Architecture. SambaNova's Reconfigurable Dataflow Unit (RDU) combines compute with a three-tier memory hierarchy (on-chip SRAM, on-package HBM, off-chip DRAM) and a software-defined dataflow compiler that fits trillion-parameter models onto a far smaller socket count than HBM-only GPUs.
Deployment. SambaNova's Argyll system runs in production at Argonne National Laboratory and SoftBank. The company is air-cooled and power-constrained — a design advantage in retrofit environments.
Networking impact. SambaNova fits big models on fewer chips, reducing scale-up density requirements; the architecture shrinks networking demand modestly. Most of the savings come from not needing the dense intra-rack scale-up fabric that GPU clusters require.
Verdict. If SambaNova reached 30% inference share, optical TAM would shrink by an estimated 15-25% on the share-equivalent basis. The probability of 30% share looks low — SambaNova is a niche/enterprise play, not a hyperscaler-class deployment story.
These are the architectures with the largest near-term share trajectories outside NVIDIA.
Google TPU "Ironwood" (v7). [S134; primary: Google Cloud blog, November 2025]. Two configurations: 256 chips and 9,216 chips per pod. Each chip delivers 4,614 TFLOPs peak; per-pod aggregate is 42.5 Exaflops. HBM is 192 GB per chip, 6x Trillium; HBM bandwidth is 7.37 TB/s per chip, 4.5x Trillium. Inter-Chip Interconnect runs 1.2 TBps bidirectional, 1.5x Trillium. A full pod spans nearly 10 MW. The 9,216-chip scale-up domain uses a 3D torus topology plus Apollo optical circuit switching — the canonical "scale-up via optical" architecture, in production since TPU v4 (2023, 4,096 chips, 48 OCS switches) 2 and now scaled 2.25x.
Networking impact (TPU): Google's OCS-based scale-up uses more transceivers, fewer electrical switches — it shifts the optical TAM mix toward optical engines, light sources, and FAU/MPO connectors and away from electrical switch ASICs. Reinforces optical TAM with a mix shift toward optics-heavy categories.
AWS Trainium 2/3. Trainium uses standard Ethernet for scale-out via the Elastic Fabric Adapter (EFA) protocol, in hundreds-of-thousands-of-chip "UltraClusters." Marvell is the named ASIC partner for Trainium silicon.
Networking impact (Trainium): Pure Ethernet scale-out. Reinforces optical TAM neutrally; pulls the mix toward open-Ethernet vendors (Arista, Marvell, Broadcom) and away from NVIDIA InfiniBand.
Microsoft Maia 100. Maia uses RoCE (RDMA over Converged Ethernet) at 24x 200 GbE per chip — a high-bandwidth scale-out profile.
Networking impact (Maia): Pure Ethernet/RoCE, reinforces optical TAM by approximately 10-15% relative to NVDA baseline at any given share level. Maia's roadmap likely tracks the Ethernet ecosystem's evolution (1.6T optics, CPO, co-packaged ASIC variants).
Meta MTIA v2. Workload-specific, optimized for ranking/recommendation rather than language; uses LPDDR not HBM; low-bandwidth-need workloads; no scale-up domain required.
Networking impact (MTIA): MTIA's narrow workload profile shrinks networking demand mildly because it eliminates the scale-up requirement entirely. Mild thesis-weakening but only relevant for the inference-ranking sub-segment.
Architecture. AMD's Instinct line (MI300X, MI325X, MI350) competes head-to-head with NVIDIA's GPUs, plus UALink (open Ethernet-PHY-based scale-up consortium) and UALoE (UALink over Ethernet) for the open-fabric stack.
Networking impact. AMD's share gain comes primarily at NVIDIA's expense; both are massive optical consumers. AMD's gain shifts the optical mix toward merchant Ethernet vendors (Arista, Broadcom, Marvell) and away from NVIDIA-specific InfiniBand and Spectrum-X. Net mildly positive (+10-15%) for optical TAM vendors who weren't already locked into NVIDIA's ecosystem.
Architecture. Gaudi 2/3 uses 24x 200 GbE of standard Ethernet per chip — 4.8 Tb/s of standard-Ethernet per accelerator. The architecture is the most "optical-friendly" in this landscape: the chip itself is effectively a switch port.
Networking impact. If Gaudi (or any future Ethernet-native architecture inheriting Gaudi's design choices) reached 30% share, it would strongly reinforce optical TAM (+15-25% over the NVIDIA baseline). The probability of Gaudi specifically reaching 30% share looks low based on Intel's Q4 2025 earnings call. The "Ethernet-native" thesis is more likely to manifest via UALoE + AMD + AWS than via Gaudi itself.
| Architecture | Per-FLOP optical demand | Thesis impact |
|---|---|---|
| Cerebras (wafer-scale) | Collapses internal interconnect (~178,000:1) | Shrink strongly if share grows |
| Groq (deterministic SRAM) | High intra-rack, low long-haul | Mix shift, neutral net |
| SambaNova (RDU + 3-tier memory) | Lower per-FLOP | Shrink modestly |
| Meta MTIA (workload-specific) | No scale-up needed | Shrink mildly in ranking sub-segment |
| Google TPU (Ironwood + OCS) | Optical-heavy scale-up | Mix shift toward transceivers, optics-up / switches-down |
| AWS Trainium (Ethernet/EFA) | Ethernet scale-out | Reinforce, mildly positive (+0-10%) |
| Microsoft Maia (RoCE) | Ethernet scale-out, 24x 200GbE | Reinforce moderately (+10-15%) |
| AMD Instinct (UALink/UALoE) | Open Ethernet-PHY scale-up + std Ethernet scale-out | Reinforce moderately (+10-15%) |
| Intel Gaudi (24x 200GbE) | Chip-as-switch | Strongly reinforce IF share materialized |
| Tenstorrent (10x 400GbE + RISC-V) | Open Ethernet | Reinforce mildly |
| Etched (Sohu) | Hardwired transformer ASIC | Neutral at plausible share |
9 of 11 non-NVIDIA architectures are Ethernet-aligned. That is the structural read: the optical thesis is robust to share shifts. Cerebras is the only architecture that genuinely cuts per-FLOP optical demand, and its 86% revenue concentration in two UAE customers caps its credible scale. Even where alternative architectures gain share, the dollars overwhelmingly flow back to the merchant-Ethernet optical ecosystem (Arista, Broadcom, Marvell, Coherent, Lumentum) rather than to NVIDIA's InfiniBand stack. The "optical wins" thesis is durable; only the mix of who wins inside optical depends on the share shift.
Two related signals, surfaced from outside the original report set, materially reinforce the networking thesis. SemiAnalysis published data from 174,264 agentic coding sessions showing that 42% of total runtime is spent on CPU work — tool execution, file edits, Bash scripts, lints — versus 58% on GPU inference 9. The claim is paywalled and self-reported, so it deserves triangulation. The triangulation holds. An academic measurement by Georgia Tech and Intel (arXiv:2511.00739, April 2026) bounds the SemiAnalysis number well inside the measured range, finding SWE-Agent at 38-65% CPU latency depending on benchmark configuration 10. Intel's Q1 2026 earnings call provided hard-money confirmation that the ratio is changing: CFO David Zinsner stated that training workloads run roughly seven-to-eight GPUs per CPU and inference runs roughly three-to-four GPUs per CPU 11 — and the broader industry framing (per TrendForce) is that today's 1:4-to-1:8 ratio is moving toward parity in agentic deployments 12. Intel implemented 10-20% server CPU price increases in Q1 2026 with 6-month lead times 13 — a behavioral confirmation that the demand is real and supply-constrained.
Arm's framing (CES 2026 briefing): AI data centers needed approximately 30 million CPU cores per gigawatt in the LLM era and now need approximately 120 million per gigawatt in the agent era — a 4x structural increase in CPU demand per unit of power 12.
The anchor anecdote is the Microsoft Fairwater data center supporting OpenAI: a 48 MW CPU+storage building supports a 295 MW GPU cluster [S401, S402, S408]. The 1:6 CPU-to-GPU power ratio at Fairwater did not exist in the pre-agentic AI architecture. Tens of thousands of CPUs are now required to process and manage the petabytes of data generated by the GPU cluster.
The chain to networking. Agentic AI is CPU-heavy because the agent loop — plan → act → reflect → revise — is sequential and tool-driven, not matmul-driven. The CPU's work in that loop is, almost entirely, network I/O: API calls to other services, retrieval-augmented-generation (RAG) queries against vector databases, file I/O against object storage, web scraping, code execution in sandboxes. Each of these is a network round-trip. AWS Nitro empirics show that 20-30% of server resources have historically been dedicated to network and storage subroutine offload 14 — and that fraction grows with agentic workload share.
This is where the DPU (Data Processing Unit) and SmartNIC (Smart Network Interface Card) layer enters. A DPU is a programmable accelerator on the server's network port that offloads networking, storage, and security work from the CPU; a SmartNIC is the same idea in a less-programmable form. The DPU layer was not in the original $154B Goldman optical-TAM forecast because Goldman scoped to optical components; but the DPU/SmartNIC layer scales directly with the CPU-driven I/O thesis.
The DPU/SmartNIC vendor map (currently a five-name landscape):
The storage I/O angle reinforces the same logic. NVMe-over-Fabric (NVMe-oF) — block storage accessed over the network rather than directly attached — turns storage I/O into yet more networking demand. NVIDIA's ICMSP (Inference Cluster Memory Scale-out Protocol) extends this by offloading the KV cache (the transformer's context-window memory) to NVMe storage accessed over Spectrum-X, with a claimed 5x tokens-per-second improvement when long-context inference is the bottleneck. The storage layer's leveraged-to-context-length companies are Pure Storage (PSTG) on the public side and VAST Data and WEKA on the private side.
Skeptical caveats. The chain holds on aggregate, but several caveats deserve mention:
Verdict. The agentic CPU thesis reinforces the networking thesis on net, with the DPU/SmartNIC layer and the storage-as-network-I/O layer as the cleanest expressions. This is one of the strongest "thesis-confirms-thesis" data points in the deliverable: a story that emerged independent of the Goldman optical-TAM framework converges with it. The agent-driven CPU load is networking demand wearing a CPU costume.
What is actually inside the $154B 2028 figure, and what is excluded? Both matter for sizing the company universe.
Included [from Goldman's $154B framework, Exhibits 1-15]:
Excluded (in other capex buckets):
The five-number summary for the headline TAM:
| Metric | Value | Marker |
|---|---|---|
| 2028 optical-networking TAM (Goldman) | $154B | 2 |
| Growth multiple vs 2026 ($15B) | 9x | 2 |
| Scale-up share of TAM | 69% / $106B | [S003, S004] |
| CPO share of TAM at 29% scale-out CPO penetration | 59% / $91B | [S005, S006] |
| Per-computing-unit scale-up dollar content (GB300 → Rubin Ultra Spec B) | 29x ($315K → $9.4M) | [S007, S008, S009] |
Discrepancy worth noting. Bernstein's framing of the same market — drawing on LightCounting data — is more conservative on the CPO ramp: copper still represents roughly half of the 1.6T interconnect market through 2029, with copper TAM growing 4x ($8B → $34B) and optics TAM growing 40x ($3B → $120B) 3. Bernstein further argues LPO shipments could surpass CPO by 2030 3, implying the value capture shifts toward lower-power pluggable form factors before the full CPO transition completes. Both views imply optical wins — the disagreement is over the mix of who wins inside optical.
The "obvious" company list for the AI networking thesis stops at NVDA, AVGO, MRVL, COHR, LITE, GLW. The differentiated value of this primer is the services tier: the companies that build, test, monitor, and operate the networking infrastructure rather than supplying its components. Every name in this tier reported (1) record Q1 2026 backlog, (2) 30-80% YoY backlog growth, and (3) explicit naming of AI DC as the dominant driver. The services tier is in a coordinated capex super-cycle that mirrors the silicon tier.
Network test and validation. Keysight Technologies (KEYS) reported Q2 FY26 revenue of $1.72B (+31% YoY) with orders of $2B+ (+56% YoY); FY26 AI-related business surpassed full-year 2025 in just half-year 19. Keysight is the dominant AI test pure-play. Viavi Solutions (VIAV) acquired Spirent's high-speed Ethernet and security businesses from KEYS (DOJ-mandated divestiture, closed October 2025); Q3 FY26 revenue $407M (+43% YoY) with Spirent product line contributing $54M in Q3 20. Spirent as a standalone entity no longer exists — test exposure now maps to KEYS plus VIAV.
Observability and monitoring. Datadog (DDOG) reported Q1 2026 revenue $1.006B (+32% YoY) — its first $1B quarter; launched GPU Monitoring, Bits AI Security Agent, and Experiments GA 21. Dynatrace (DT) ARR surpassed $2B with domain-specific AI agents positioned as the control plane for agentic workloads 22. Inside Cisco, ThousandEyes (network path visibility, acquired 2020) and Splunk (acquired 2024) provide the embedded observability layer. The private specialists are Selector AI (Santa Clara, $375M valuation) and Kentik (San Francisco, $133M raised) [S317, S318] — the two scaled pure-plays in AI-cluster-specific observability beyond generic APM (Application Performance Monitoring).
DC commissioning and Cx services — the heart of the services-tier capex super-cycle. Six public names with aggregate backlog exceeding $90B, all naming AI DC explicitly:
Fiber managed-service providers and DCI specialty. Lumen (LUMN) closed approximately $13B of Private Connectivity Fabric deals with Microsoft and Meta during FY25, with the stock re-rating from about $1 in mid-2024 to about $12 in late 2025 on the AI-fiber-asset thesis 29. Cogent (CCOI) Q4 2025 wavelength revenue was $12.1M (+73.7% YoY) 30. Uniti (UNIT) post-Windstream operates 240K route miles plus FTTH (Fiber To The Home); it signed a 20-year $100M hyperscaler IRU (Indefeasible Right of Use) with a total hyperscaler funnel of $1.5B 31. Crown Castle is out of fiber — CCI sold fiber and small cells for $8.5B on May 1 2026; Zayo bought the fiber business for $4.25B EV [S239, S240]. Crown Castle is now tower-only.
Power infrastructure — the throughput constraint. Eaton (ETN) reported Q1 2026 data-center orders +240% YoY, with 10 solid-state-transformer projects in pilot with hyperscalers 32. Vertiv (VRT) backlog $12.45B (+80.8% YoY) 33. nVent (NVT) record revenue $1.24B (+53% total, +34% organic) with $2.3B entering backlog primarily for large liquid-cooling orders 34.
The structural observation. The market understands COHR/LITE as picks-and-shovels. It does not yet uniformly recognize that the services tier has equal or greater absolute backlog visibility — FIX, PWR, EME, VRT, ETN combined offer well over $100B of contracted forward revenue. The "picks-and-shovels of the picks-and-shovels" trade is to the services tier, not just the optical components.
The Goldman $154B TAM rests on a specific consensus path for token demand (Decoding Agentic Economy report, May 5 2026 [S059, S061, S083]) plus Goldman's own assumptions about scale-up density and CPO penetration. The question the primer answers here, qualitatively: if token demand grows 50% faster than the consensus path, where in the networking stack does the marginal dollar land?
The mechanism that makes networking disproportionately leveraged: networking is the layer where the dollar content per unit of compute is already growing 29x per computing unit [S007, S008, S009]. A 50% overshoot in token demand does not simply scale that 29x linearly — it pulls forward CPO penetration (29% at 2028 baseline → potentially 40-50% in the overshoot case) because the alternative (more pluggables) is power-constrained. The headline TAM bends upward in three ways:
Where the thesis weakens in the overshoot. If the marginal token comes from a single architectural change (for example, hyperscalers converging on Cerebras-style wafer-scale or SambaNova-style dataflow), then the per-FLOP optical demand falls and the headline TAM compresses. But as §4 documented, 9 of 11 non-NVIDIA architectures are Ethernet-aligned — the share-shift risk is the smaller risk. The larger risk is workload composition: if simple-tool-call agents dominate the population over RAG/coding agents, the agentic-CPU amplification is muted.
Net read. In the upside scenario (token demand 50% above consensus, agentic-mix shifts toward CPU-heavy work), the networking layer's TAM grows by more than the 50% overshoot would suggest — somewhere in the range of 60-80% on the optical components, with disproportionate growth in DCI/scale-across, CPO penetration acceleration, and the DPU/SmartNIC layer. The headline TAM bends from $154B toward $200B+ in 2028 under that scenario. The bear case (workload mix shifts to simple-tool-call, share concentrates in CPU-light architectures) bends the headline back toward $130-140B. Both cases preserve the central claim that networking is the most-leveraged layer of the AI-DC capex curve.
The pages above contain the layer-by-layer thesis; this section maps the layers to specific names. A trades on a tab is reserved for follow-on deliverables; this section's purpose is to give the reader a usable shortlist by layer with a one-line thesis per name.
Layer 1 — Chip and platform. NVIDIA (NVDA, ~$5.2T) — networking now ~20% of data-center revenue; Q4 FY26 networking $10.98B (+263% YoY) [S200, S201]. Broadcom (AVGO, ~$1.96T) — Tomahawk-6 102.4 Tb/s; Q1 FY26 AI revenue $8.4B (+106% YoY); FY27 target $100B+ across six named custom-XPU customers [S202, S203]. Marvell (MRVL, ~$172B) — Trainium silicon partner; Q4 FY26 data-center revenue $1.65B (74% of total) [S204, S205]. Arista (ANET, ~$218B) — cleanest pure-play AI-networking equipment; Q1 2026 revenue $2.71B (+35% YoY); FY26 AI networking target raised to $3.25B [S206, S207]. Cisco (CSCO, ~$475B) — Silicon One + ThousandEyes + Splunk; FY26 hyperscaler AI orders guided to ~$9B [S208, S209].
Layer 2 — Optical components. Coherent (COHR, ~$58B) — InP vertical integration, NVIDIA partner [S210, S211]. Lumentum (LITE, ~$76B) — Q3 FY26 revenue $808M (+90% YoY), record cloud transceiver shipments [S212, S213]. Fabrinet (FN, ~$24B) — outsourced optical manufacturing pass-through [S214, S215]. Astera Labs (ALAB, ~$26B) — 95% AI-DC mix, Scorpio X-Series scale-up fabric switch [S216, S217]. Credo (CRDO, ~$22B) — AEC pure-play; Jefferies April 2026 sized AEC TAM at $3-5B by 2027-29 [S218, S219]. MACOM (MTSI, ~$18B) — PAM4 + LPO [S220, S221]. Semtech (SMTC) — CopperEdge ACC, smaller CRDO comp 35.
Layer 3 — Cabling and connectors. Amphenol (APH) — Q1 2026 revenue $7.62B (+58% YoY); IT datacom 41% of total; closed $10.5B CommScope CCS acquisition; now THE combined fiber + copper + DC interconnect pure-play [S223, S227]. TE Connectivity (TEL) — Q2 FY26 AI infrastructure revenue $900M → $2.3-2.4B FY26 (+155%) 36.
Layer 4 — Fiber. Corning (GLW, ~$139B) — Q1 2026 Optical Communications revenue $1.85B (+36% YoY); two new hyperscaler agreements signed in Q1 similar in size to the existing ~$6B Meta multi-year deal [S225, S226].
Layer 5 — PCB and substrate (Asian-listed, US-investor friction). Unimicron (3037.TW) — sold out through 2027 [S230]. Ibiden (4062.T) — announced ¥500B AI substrate capex in February 2026 37. Ajinomoto (2802.T) — ABF film monopoly, 50%+ margins, implemented 30% price increase effective Q3 2026 38.
Layer 6 — DC interconnect, DCI, fiber MSPs. Equinix (EQIX, ~$106B) — Fabric bookings +70% YoY; 5,800 net new interconnections in Q1 [S231, S232]. Digital Realty (DLR, ~$68B) — 200 MW AI inference lease in Charlotte (largest in company history); backlog record $1.8B [S233, S234]. Lumen (LUMN) — ~$13B PCF deals with Microsoft and Meta in FY25 29. Cogent (CCOI, ~$1B) — wavelength revenue +73.7% YoY [S236, S237]. Uniti (UNIT) — post-Windstream; hyperscaler funnel $1.5B 31.
Layer 7a — Network test. Keysight (KEYS) — FY26 AI revenue surpassed full-year 2025 in half-year 19. Viavi (VIAV) — Spirent HSE acquirer; KEYS competitor 20.
Layer 7b — Observability. Datadog (DDOG, ~$71B) — first $1B quarter; GPU Monitoring + Bits AI Security Agent [S243, S244]. Dynatrace (DT) — ARR > $2B; AI-control-plane positioning 22.
Layer 7c — DC commissioning. Comfort Systems USA (FIX) — backlog $12.45B (+80.8% YoY) 23. EMCOR (EME) — RPO $15.62B (+32.9% YoY) [S247, S264]. Quanta Services (PWR) — backlog $48.5B; investing in transformer manufacturing 25. MasTec (MTZ) — backlog $20.3B 26. Dycom (DY) — backlog $9.5B 27. IES Holdings (IESC) — backlog $3.9B (+62%) 28. Tutor Perini (TPC) — backlog $19.8B, emerging DC exposure in specialty contracts 39.
Layer 7d — Power infrastructure. Eaton (ETN, ~$156B) — Q1 2026 DC orders +240% YoY 32. Vertiv (VRT, ~$131B) — backlog $12.45B [S253, S254]. Schneider Electric (SBGSF / SU.PA, ~$172B) — Data Centers & Networks 30% of revenue 40. nVent (NVT) — Q1 2026 record revenue +53%; liquid cooling concentration 34. Generac (GNRC, ~$16B) — pivoting to integrated DC; $1B DC revenue target by 2028 41.
Layer 8 — DPU / SmartNIC (the §5 layer not in Goldman's outline). NVDA BlueField-4, AMD Pensando (inside AMD), MRVL Octeon (inside MRVL), Intel IPU (inside INTC), AWS Nitro (in-house at AMZN). Astera Labs's Scorpio X-Series fits at the boundary between scale-up fabric and DPU functionality 42.
Private companies (selected).
Photonic interconnect: Ayar Labs (Santa Clara, $3.75B val, $870M raised — silicon-photonics chiplets for AI scale-up) [S300, S301]. Lightmatter (Mountain View, $4.4B val, $850M raised — photonic compute + interconnect) [S302, S303]. Celestial AI ($1B+ val, $515M+ raised — acquired by Marvell, closed February 2026, now part of MRVL story) [S079, S304, S305]. Avicena ($120M raised — micro-LED optical interconnect) 43. Xscape Photonics ($95M raised, NYC — comb-laser-based interconnect) 44. Quintessent ($11.5M seed, Santa Barbara — quantum dot lasers) 45. Luminous Computing 46. Akhetonics (Germany, €6M seed) 47. Salience Labs (Oxford, UK) 48. Lightelligence (Shanghai — IPO'd on HKEX April 2026; now a public name) 49.
Fiber MSP private: Zayo (Boulder, EQT/DigitalBridge — $14.3B take-private; acquired Crown Castle Fiber Solutions for $4.25B EV May 2026) [S324, S337]. EXA Infrastructure (London, I Squared Capital — $2.15B carve-out, absorbed Aqua Comms) [S325, S326]. euNetworks (London, Stonepeak — 600+ EU DCs) 50.
DC commissioning private: Cupertino Electric, Rosendin Electric, Holder Construction — all private, employee-owned; real AI-DC revenue exposure but no exit path. [S333, S334, S335].
Specialty cooling private: Submer, Iceotope, Green Revolution Cooling. [S321, S322, S323].
AI observability private: Selector AI ($375M val), Kentik ($133M raised) [S317, S318].
Sub-Rosendin tier MEP, AI-cluster observability stealth, photonic-switch SiPho design houses — flagged for follow-up Grata queries; the private universe in those layers is thinner-than-expected in public data.
M&A signal — the strategic-bet pattern. Six absorbing M&A events in the 12 months ending May 2026: NVIDIA/Run:ai $700M, CoreWeave/Weights & Biases $1.7B, Ciena/Nubis $270M 51, Credo/Hyperlume, Astera/aiXscale 52, Marvell/Celestial AI ($1B+) 53. This is the tell on where strategics are placing their bets — the optical-interconnect private space is consolidating into the public-stack players.
Companion reading. This primer extends and is read alongside the AI-infra market map, the DC archetype BOM memo, the agentic AI primer, and the token primer.
Counter-thesis (Bernstein, May 2026; LightCounting market data, ongoing): the optical TAM expansion is real but the timing and mix are wrong. Copper survives as approximately half of the 1.6T interconnect market through 2029, growing 4x ($8B → $34B); optical grows 40x ($3B → $120B) but on a smaller base than Goldman's 9x-from-$15B framing suggests 3. LPO shipments could surpass CPO by 2030 3, meaning the value capture shifts toward lower-power pluggable form factors before the full CPO transition completes. If Bernstein is right, the dollars flow to PCB/CCL (Victory Giant, WUS, EMC), ABF substrate (Unimicron, Ibiden, Ajinomoto), and AEC (Credo, Semtech) rather than to CPO optical engines and chip-designer-owned packaging. The directional bet — that networking is the leveraged layer — is the same; the names that win are different. The risk is overweighting the chip-designer-and-CPO trade (Broadcom, NVIDIA, Marvell, TSMC, Coherent CPO business, Lumentum CPO business) at the expense of the substrate-and-copper trade (Ajinomoto, Unimicron, Credo, Amphenol).
The numbered Sources list below carries the full citation set; every [S###] marker in the text resolves to a source with a verbatim quote, URL, source class, and publication date. The headline anchors are Goldman Sachs's "Optical Networking: The Next Mega Trend in AI Infrastructure" (the $154B TAM forecast), the Bernstein 97-page interconnect report (the per-GPU dollar-content and copper-survival framing), and the PANews bottleneck-transmission article.